VLSI - Essential timing checks

VSD – Static Timing Analysis – I

VLSI – Essential timing checks
Notes de 4,4 sur 5
2 504 Avis
6 921  Sessions

Ce que vous allez apprendre dans ce cours

Détails

DescriptionStatic timing analysis comprises broadly for timing checks, constraints and library. Having all of them in a single course makes it bulky. So we decided to have it in 3 parts and this is part I – Essential timing checks. This course will give an eagle’s eye to every timing check that is being performed in current industries for sign-off. This will also introduce you to basic terminologies for timing, which are needed for advanced courses on STA.
Timing comes at every step of physical design flow, but in this course, we primarily focus on signoff timing i.e. looking into each and every corner of design for any timing violations
The course starts from very basic and gradually takes you to an advanced level at an intermediate pace. So no questions on you missing any details
Hope you enjoy learning this course in the same way we enjoyed making them.
Happy Learning !!À qui ce cours s’adresse-t-il ?Course starts from basic timing path to advanced latch checks, so basics of flipflops should be enoughAfficher plusAfficher moins

VLSI - Essential timing checks

19,99 €
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