Description
Welcome to first ever QnA webinar on RTL synthesis using Yosys. This webinar was conducted on 19th May, 2018 with Clifford Wolf
Its a Q&A webinar on RTL Synthesis, by Clifford Wolf. Clifford is architect of Yosys which is a framework for Verilog RTL synthesis. It currently has extensive Verilog-2005 support and provides a basic set of synthesis algorithms for various application domains.
Clifford will be answering 23 queries on RTL synthesis. TOP23 query submissions are directly eligible for certificates from our company VSD Corp. Pvt. Ltd.
Note of Appreciation I have worked with Clifford in my course on TCL programming Part 1 & 2, and really Thank him for all his guidance for making of TCL programming course.
Clifford has more than 20+ years of experience and is been known the Architect and Father of Yosys, OpenSCAD (now maintained by Marius Kintel), SPL (a not very popular scripting language), EmbedVM (a very simple compiler+vm for 8 bit micros), Lib(X)SVF (a library to play SVF/XSVF files over JTAG), ROCK Linux (discontinued since 2010)
All the best and happy learning.
À qui ce cours s’adresse-t-il ?
Anyone who wants to enter VLSI front-end design field should take this course, as this course will answer lot of questions related to synthesis in general
Anyone looking to start using opensource tool Yosys for synthesis
Anyone curious to know what’s happening in the world of RTL synthesis
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