Description
Learn STA and Timing Constraints Concepts Deeply by vlsideepdive.
We are on a mission to inspire and develop people to achieve their goals in professional life. We enable people to learn deeply through bite-sized, interactive learning experiences. Our courses are structured and designed by leading experts in their respective fields.
Course Created by Industry Expert: Vikas Sachdeva
Vikas Sachdeva is a semiconductor design professional with more than 17 years of experience in the VLSI Industry. He was worked in the design, development, and deployment of multiple static and constraints products.
The webinar covers all basic concepts in Static Timing Analysis and Timing Constraints
Introduction to Static Timing Analysis
Timing Paths
Startpoint, Endpoint, Combinational Logic
Setup and Hold Check Definition
Understanding details of setup slack calculation
Multiple types of Timing Paths
Design Rule Checks
Timing checks on Async Pins
Clock Gating Checks
Timing Latches
STA in presence of Multiple Clocks
Timing Arcs
Cell Delays and Models
Impact of clock network on STA
Understanding Text Report in STA
Overview of SDC
Clock and Generated Clock Definitions
Clock Groups
Clock Characteristics Specification
Port Delays
Timing Exceptions
Other SDC commands
Learn deeply
vlsideepdive replaces traditional books & lecture videos with hands-on, interactive lessons. It’s a better (and more fun) way to learn.
For any experience level– Get started as a beginner with the fundamentals, or deep-dive right into advanced concepts. We have courses for ambitious people of all experience levels.
Master essential concepts – Build confidence with hands-on learning. You will get to see concepts visually, interact with the key ideas and solve challenging problems that get you to really think and learn deeply.
Stress less, learn better – Enjoy fun storytelling, guided problem solving, here your natural curiosity will automatically drive you.
À qui ce cours s’adresse-t-il ?
College students, beginners and professionals working in VLSI field
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