DescriptionThis webinar aims at design of 1024×32 SRAM cell array (32Kbits or 4KB) with a configuration of 1.8 V operating voltage and access time less than 2.5ns using Google SkyWater SKY130 PDKs and OpenRAM memory compiler.Static Random-Access Memory (SRAM) has…
Description If you are STA engineer or PNR engineer or CTS engineer or, in general, a physical designer or Synthesis engineer, you must have definitely come across the word ‘Library’. This course explains you, in detail, what it exactly means. …
Description Hi Guys, Did you just get a job interview appointment with your dream company, actively preparing and nervously waiting for the time to come? Either it is a phone screening, or onsite interview, don’t be nervous! You are so…
Description This webinar provides detail about General Purpose Bandgap Reference. The basic working principle of Bandgap reference circuits is explained . The circuit implementation is discussed and the issues with each implementation style is mentioned. Index Terms—Bandgap Reference, CTAT, PTAT,…
Description Most of the signals around us, in the world we live in are not digital in nature, rather they are analog. The digital systems can understand only digital signals, not analog. Hence, it becomes important to interface the digital…
Description Hi Guys, Did you just get a job interview appointment with your dream company, actively preparing and nervously waiting for the time to come? Either it is a phone screening, or onsite interview, don’t be nervous! You are so…
DescriptionWhether you are a fresher or experienced professional who wants to refresh your concepts, this is the right place for you to start. Lectures are organised topic based so that each lecture is more or less independent of each other,…
Description The webinar aims to do analog layout design of a 10-bit potentiometric Digital to Analog Converter, from scratch, using Magic and Sky130 PDKs. The target is to layout and generate GDS for 10-bit potentiometric DAC with 3.3v analog voltage,…
DescriptionPerformance, Power and Area are the three main pillars of the Chip Design, Crosstalk can hamper all three. Crosstalk is the interference caused due to communication between the circuits Lets learn to » HOW TO REDUCE CROSSTALK ? » to…
Description Welcome to first ever QnA webinar on RTL synthesis using Yosys. This webinar was conducted on 19th May, 2018 with Clifford Wolf Its a Q&A webinar on RTL Synthesis, by Clifford Wolf. Clifford is architect of Yosys which is…
