Description If you are STA engineer or PNR engineer or CTS engineer or, in general, a physical designer or Synthesis engineer, you must have definitely come across the word ‘Library’. This course explains you, in detail, what it exactly means. …
Description This course is a follow-up course of « VLSI Academy – Clock tree synthesis – Part 1 ». So its highly recommended to go through Part 1 of clock tree synthesis Clock is a critical part of any VLSI chip, and this course…
Description JOIN VSDOpen2020 and be a part of open-source revolution !! VSDOpen 2020 was bigger and better !! VSDOpen 2020 had LIVE Tutorial Session for first 3 days VSDOpen 2020 showcased open-source analog IP’s VSDOpen 2020 was for 4-days View…
DescriptionAs promised, again, TCL Programming – Part 2 course has been pre-launched with 5 videos. Many more to come, as always. This course is a unique mixture of TCL programming being used in manipulating output EDA tools, creating EDA commands (like…
Description First, let’s define better? Better in terms of Power. Performance and Area Every VLSI engineer, an RTL architect, or Lead Synthesis Engineer, or Senior Physical Designer, or Director of Signoff timing analysis – practically everyone is doing timing ECO…
DescriptionStatic timing analysis comprises broadly for timing checks, constraints and library. Having all of them in a single course makes it bulky. So we decided to have it in 3 parts and this is part I – Essential timing checks.…
DescriptionThis time …. Its more personal You have been very supportive for all these 6 years and I would like to « Thank You » from the bottom of my heart Now its time to enter your hearts and minds, so we…
DescriptionPerformance, Power and Area are the three main pillars of the Chip Design, Crosstalk can hamper all three. Crosstalk is the interference caused due to communication between the circuits Lets learn to » HOW TO REDUCE CROSSTALK ? » to…
Description Welcome to first ever QnA webinar on RTL synthesis using Yosys. This webinar was conducted on 19th May, 2018 with Clifford Wolf Its a Q&A webinar on RTL Synthesis, by Clifford Wolf. Clifford is architect of Yosys which is…
Description The course is designed in the form of micro-videos, which delivers content in the form of Info-Graphics. It is designed for self-learning and will help to polish the Industrial skills in VLSI World. This course will cover end-to-end description…
