Description
This course describes how the PNR of an analog IP, 2:1 analog multiplexer is carried out by opensource EDA tools, OpenLANE. It also discusses the steps to modify the current IP layouts in order to ensure its acceptance by the EDA tools
Mixed signal SoC is a chip which contains both analog and digital blocks. The designers are adding more analog circuitry and increasing their complexities day by day. Not only that, they also contain digital control logic. As the process nodes shrink, the demand for integration grows. A divide and conquer approach is followed, where the analog and digital structures were dealt with separately. Usually, an analog IP (Intellectual Property) is bought as black- box
To implement a RTL-to-GDS flow for mixed signal SoC, there is need to establish communication between the analog and digital blocks. For this integration to happen, hierarchical level of abstraction with either analog or digital as top level is required. In order to carry out this task, OpenROAD project can be utilized
Hope you enjoy the session. Any constructive feedback is appreciated
Future Work
To include custom LIB for macro and include timing constraints.
To perform PNR on macro of triple-height or more
Acknowledgement
Kunal Ghosh, Co-founder, VSD Corp. Pvt. Ltd
Openlane team, Efabless corporation
Tim Edwards, Senior Vice President of Analog and Design at efabless corporation
Nickson Jose, VLSI Engineer
Prithivi Raj K, National Institute of Technology Tiruchirapalli
À qui ce cours s’adresse-t-il ?
Students looking for a platform to enter into Physical design world
Experts looking forward to explore Macro based OpenLANE flow
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